1. Field of the Invention
Generally, the present disclosure relates to the fabrication of integrated circuits, and, more particularly, to P-channel transistors comprising a high-k metal gate electrode formed in an early manufacturing stage.
2. Description of the Related Art
The fabrication of complex integrated circuits requires the provision of a large number of transistor elements, which represent the dominant circuit element in complex integrated circuits. For example, several hundred millions of transistors may be provided in presently available complex integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently the most promising approach due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. In CMOS circuits, complementary transistors, i.e., P-channel transistors and N-channel transistors, are used for forming circuit elements, such as inverters and other logic gates to design highly complex circuit assemblies, such as CPUs, storage chips and the like. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, or generally a field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions and an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed in the vicinity of the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The continuing shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. For example, highly sophisticated dopant profiles, in the vertical direction as well as in the lateral direction, are required in the drain and source regions to provide low sheet and contact resistivity in combination with a desired channel controllability.
With a reduced channel length, generally, a shallow dopant profile may be required in the drain and source regions, while nevertheless a moderately high dopant concentration is required in view of providing the low series resistance, which in turn results in a desired drive current in combination with a reduced channel resistance. A shallow dopant profile in combination with a low overall drain and source resistance is typically realized by forming so-called drain and source extension regions, which may represent extremely shallow doped areas extending below the gate electrode structure so as to appropriately connect to the channel region. On the other hand, an increased lateral offset with respect to the channel region is adjusted on the basis of appropriately dimensioned sidewall spacers, which are used as implantation masks for forming the actual drain and source regions with a desired high dopant concentration and with an increased depth compared to the drain and source extension regions. By appropriately selecting the size of the drain and source extension regions, channel controllability may be maintained for very short channel transistors while also providing a desired low overall series resistance in connecting the drain and source regions to the channel region. Consequently, for a desired performance of sophisticated transistor elements, a certain degree of overlap of the drain and source extension regions with the gate electrode is desirable in order to obtain a low threshold voltage and a high current drive capability. The overlap of the drain and source extension regions with the gate electrode gives rise to a specific capacitive coupling that is also referred to as Miller capacitance. Typically, a desired Miller capacitance is adjusted on the basis of implantation processes in which the drain and source dopants may be introduced in order to form the basic configuration of the drain and source extension regions, wherein the final shape of these regions may then be adjusted on the basis of a sequence of anneal processes in which implantation-induced damage are re-crystallized and also a certain degree of dopant diffusion may occur, thereby finally determining the resulting Miller capacitance.
Upon continuously reducing the channel length of field effect transistors, generally, an increased degree of capacitive coupling is required in order to maintain controllability of the channel region, which may typically require an adaptation of a thickness and/or material composition of the gate dielectric material. For example, for a gate length of approximately 80 nm, a gate dielectric material based on silicon dioxide with a thickness of less than 2 nm may be required in high speed transistor elements, which may, however, result in increased leakage currents caused by hot carrier injection and direct tunneling of charge carriers through the extremely thin gate dielectric material. Since a further reduction in thickness of silicon dioxide-based gate dielectric materials may increasingly become incompatible with thermal power requirements of sophisticated integrated circuits, other alternatives have been developed in increasing the charge carrier mobility in the channel region, thereby also enhancing overall performance of field effect transistors. One promising approach in this respect is the generation of a certain type of strain in the channel region, since the charge carrier mobility in silicon strongly depends on the strain conditions of the crystalline material. For example, for a standard crystallographic configuration of the silicon-based channel region, a compressive strain component in a P-channel transistor may result in a superior mobility of holes, thereby increasing switching speed and drive current of P-channel transistors. The desired compressive strain component may be obtained according to well-established approaches by incorporating a strain-inducing semiconductor material, for instance in the form of a silicon/germanium mixture or alloy, in the active region of the P-channel transistor. For example, after forming the gate electrode structure, corresponding cavities may be formed laterally adjacent to the gate electrode structure in the active region and may be refilled with the silicon/germanium alloy which, when grown on the silicon material, may have an internal strained state, which in turn may induce a corresponding compressive strain component in the adjacent channel region. Consequently, a plurality of process strategies have been developed in the past in order to incorporate a highly strained silicon/germanium material in the drain and source areas of P-channel transistors, which may, however, also require corresponding adaptations in view of obtaining a desired lateral and vertical dopant profile for the drain and source regions and the corresponding extension regions as, for instance, boron which is frequently used as a P-type dopant species, may have a significantly different diffusion behavior in a silicon/germanium material compared to a silicon-based material. That is, in a silicon/germanium material having a germanium concentration of approximately 20 atomic percent or higher, the diffusivity of the boron species is significantly less compared to a silicon species, which may have to be taken into consideration when adjusting the overall transistor characteristics. For example, typically, the drain and source extension regions may be formed so as to be located within a silicon material so that the Miller capacitance may be adjusted on the basis of the diffusion characteristics in silicon material so as to obtain the required overlap of the drain and source extension regions with the gate electrode structure without having to take into consideration the reduced diffusivity in a silicon/germanium material.
During the continuous reduction of the critical dimensions of transistors, an appropriate adaptation of the material composition of the gate dielectric material has been proposed such that, for a physically appropriate thickness of a gate dielectric material, i.e., for reducing the gate leakage currents, nevertheless, a desired high capacitive coupling may be achieved. Thus, material systems have been proposed which have a significantly higher dielectric constant compared to the conventionally used silicon dioxide-based materials, silicon oxynitride materials and the like. For example, materials including hafnium, zirconium, aluminum and the like may have a significantly higher dielectric constant and are therefore referred to as high-k dielectric materials, which are to be understood as materials having a dielectric constant of 10.0 or higher when measured in accordance with typical measurement techniques. As is well known, the electronic characteristics of the transistor elements also strongly depend on the work function of the gate electrode material which influences the band structure of the semiconductor material in the channel region separated from the gate electrode material by the gate dielectric material. In well-established polysilicon/silicon dioxide-based gate electrode structures, the corresponding threshold voltage, that is strongly influenced by the gate dielectric material and the adjacent electrode material, is adjusted by appropriately doping the polysilicon material in order to appropriately adjust the work function of the polysilicon material at the interface between the gate dielectric material and the electrode material. Similarly, in gate electrode structures including a high-k gate dielectric material, the work function has to be appropriately adjusted for N-channel transistors and P-channel transistors, respectively, which may require appropriately selected work function adjusting metal species, such as lanthanum for N-channel transistors and aluminum for P-channel transistors. For this reason, corresponding metal-containing conductive materials may be positioned close to the high-k gate dielectric material in order to form an appropriately designed interface that results in the target work function of the gate electrode structure. In many conventional approaches, the work function adjustment may be performed at a very late manufacturing stage, i.e., after any high temperature processes, which may require the replacement of a placeholder material of the gate electrode structures, such as polysilicon, and the incorporation of appropriate work function adjusting species in combination with an electrode metal, such as aluminum and the like. In this case, however, very complex patterning and deposition process sequences may be required on the basis of gate electrode structures having critical dimensions of 50 nm and significantly less, which may result in severe variations of the resulting transistor characteristics.
Therefore, other process strategies have been proposed in which the work function adjusting materials may be applied in an early manufacturing stage, i.e., upon forming the gate electrode structures, wherein the corresponding metal species may be thermally stabilized and encapsulated in order to obtain the desired work function and thus threshold voltage of the transistors without being unduly influenced by the further processing. For this purpose, it turns out that, for P-channel transistors, an appropriate adaptation of the band gap of the channel semiconductor material may be required in order to appropriately set the work function of the P-channel transistors. For this reason, frequently, a so-called threshold adjusting semiconductor material, for instance in the form of a silicon/germanium mixture, may be formed on the active regions of the P-channel transistors prior to forming the gate electrode structures, thereby obtaining the desired offset in the band gap of the channel semiconductor material. Although this concept is a promising approach for forming sophisticated high-k metal gate electrode structures in an early manufacturing stage, the adjustment of the transistor characteristics may be difficult to be achieved on the basis of conventional strategies due to the presence of the channel silicon/germanium material, as will be described in more detail with reference to FIGS. 1a-1d. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a substrate 101 and a silicon-based semiconductor layer 102. The semiconductor layer 102 comprises a plurality of “active” regions, such as a semiconductor region 102A, which is laterally delineated by an isolation structure 102B, for instance provided in the form of a shallow trench isolation. The shallow trench isolation 102B is comprised of any appropriate insulating material, such as silicon dioxide, silicon nitride and the like. It should be appreciated that an active region, such as the semiconductor region 102A, is to be understood as a semiconductor region in and above which one or more transistors are to be formed. For instance, a transistor 150 in an early manufacturing stage represents a P-channel transistor of the device 100, which is to be formed on the basis of the semiconductor region 102A. Consequently, in this manufacturing stage, the transistor 150 comprises a well dopant species (not shown) which imparts a desired basic conductivity type to the semiconductor region 102A, for instance an N-type conductivity. Furthermore, as previously explained, a threshold adjusting semiconductor material 103 in the form of a silicon/germanium alloy, i.e., in the form of a crystalline silicon/germanium mixture, is formed on the semiconductor material 102A and is to be considered as a part of the active region of the transistor 150. The silicon/germanium material 103, which is also referred to as a threshold adjusting semiconductor material, has a specific thickness and material composition, i.e., germanium concentration, in order to obtain a desired band gap offset, as previously discussed. For instance, the material 103 may have a thickness of approximately eight to several tenths of angstrom with a germanium concentration of approximately 20-30 atomic percent. Moreover, the transistor 150 comprises a gate electrode structure 160, which in turn comprises a gate dielectric material, for instance in the form of a first layer 161 and a second layer 162, such as a silicon oxynitride material as the layer 161 in combination with a high-k dielectric material layer such as hafnium oxide, a silicon oxynitride/hafnium mixture and the like. Furthermore, a conductive cap material 164, which typically also comprises a work function adjusting species, such as aluminum, is formed above the gate dielectric material 162, followed by a further electrode material 165, such as amorphous or polycrystalline silicon. It should be appreciated that in particular the cap material 164 including the work function adjusting species may be provided in the form of a material layer stack including several materials, such as titanium nitride, aluminum and the like. In other approaches, the work function metal species may be incorporated in at least one of the dielectric materials 161 and 162, for instance in the material 162, thereby generating charges, such as dipole charges therein. In this case, the cap material may be provided in the form of any desired electrode material. Moreover, the gate electrode structure 160 comprises a spacer structure 166, for instance comprising an oxide liner (not shown) in combination with a silicon nitride spacer element, thereby reliably confining the sidewalls of sensitive materials, such as the layers 161, 162 and 164. Moreover, a dielectric cap material 157, such as a silicon nitride material, is formed on top of the electrode material 165.
The semiconductor device 100 as illustrated in FIG. 1a may be formed on the basis of any appropriate manufacturing techniques. For example, the active region 102A is formed by providing the isolation structure 102B and implanting a desired well dopant species. Thereafter, the threshold adjusting semiconductor material 103 is formed by epitaxial growth techniques, for instance by forming a mask layer, such as a silicon dioxide layer, on active regions which do not require the material 103 and by performing a selective deposition process in which material deposition may be substantially restricted to exposed crystalline silicon areas, such as the semiconductor region 102A. Next, any mask materials may be removed and the complex gate layer stack may be formed by appropriate deposition techniques. Thereafter, a complex lithography and patterning process sequence is applied to form the materials 165, 164, 162 and 161 with the desired gate length, i.e., in FIG. 1a, the horizontal extension of these materials, which may be 50 nm and less in sophisticated semiconductor devices. Furthermore, also the dielectric cap layer 167 may be patterned together with the electrode material 165. Next, cavities 102C are to be formed in the active region 102A so as to incorporate a strain-inducing silicon/germanium alloy, as discussed above. For this purpose, a spacer layer may be deposited, for instance in combination with providing a silicon oxide liner, and the spacer material may be selectively patterned into the spacer element 166, while in other areas in which the strain-inducing semiconductor alloy may not be required, the spacer layer may be preserved. Thereafter, appropriate etch techniques are applied so as to etch through the exposed portion of the material 103 and into the region 102A, thereby forming the cavities 102C.
FIG. 1b schematically illustrates the device 100 with a silicon/germanium alloy 104 formed in the semiconductor region 102A, thereby imparting a compressive strain to a channel region 151. The semiconductor material 104 may be formed by a selective epitaxial growth process, wherein a germanium concentration of up to 35 atomic percent or more in accordance with available deposition techniques is achieved, thereby obtaining a desired high compressive strain component. Consequently, the material 104 is selected so as to provide the desired strain component, while the threshold adjusting material 103, which represents a part of the channel region 151, results in a desired band gap offset in order to obtain the desired threshold voltage in combination with the work function of the material layer 164 in combination with the characteristics of the gate dielectric materials 161, 162.
FIG. 1c schematically illustrates the semiconductor device 100 when performing an implantation process 105 in order to incorporate drain and source dopant species into the semiconductor region 102A in order to form the basic configuration of drain and source extension regions 152. Typically, a boron implantation species is introduced during the implantation process 105, wherein the implantation dose is selected such that a desired high concentration is obtained for the drain and source extension regions 152 in order to reduce the overall resistivity, yet avoiding undue hot carrier injection and the like. Moreover, the implantation energy is controlled so as to obtain a desired reduced penetration depth as required for the overall transistor operation. Consequently, the drain and source extension regions 152 are formed within the material 104 and within a portion of the material 103, which, however, may result in a significantly different diffusion behavior compared to a silicon material, which is still below the threshold adjusting semiconductor material 103. Consequently, upon using similar implantation dose values as are typically applied for sophisticated transistor elements based on a polysilicon/silicon oxynitride gate electrode structure, i.e., without the semiconductor material 103, the reduced diffusivity of the dopants in the drain and source extension regions 152 as implanted may result in a reduced dopant diffusion and thus in a reduced overlap with the gate electrode structure 160. Due to the reduced Miller capacitance, the corresponding threshold voltage and other transistor characteristics may, therefore. result in reduced overall performance of the transistor 150. Consequently, in some approaches, the implantation dose during the process 105 may be increased, for instance up to two or three times the dose of conventional sophisticated polysilicon/silicon oxynitride devices, in order to compensate for the reduced diffusion activity. After the implantation process 105 and after any halo implantation processes, i.e., an implantation process for introducing a dopant species into the semiconductor region 102A below the channel region 151 so as to locally increase the corresponding dopant concentration, the processing is continued by forming an additional sidewall spacer structure that provides an increased lateral offset for performing further implantation processes in order to implant the drain and source regions into the active region 102A.
FIG. 1d schematically illustrates the device 100 with a sidewall spacer structure 154 and drain and source regions 153 formed on the basis of the structure 154, as indicated above. Moreover, the device 100 is subjected to one or more anneal processes 106 in order to provide the desired degree of dopant diffusion and also activate the dopants. For instance, appropriate spike anneal techniques, possibly in combination with extremely fast laser-based or flashlight-based anneal processes, are applied. Consequently, the final dopant profile is obtained during the anneal process or processes 106 wherein, however, as discussed above due the presence of the material 103 that reduces the diffusivity of the P-type dopant species, a reduced overlap of the extension regions 152 may be obtained, as indicated by the solid line 152R, if a standard implantation dose has been used during the implantation process 105 of FIG. 1c. On the other hand, a desired increased overlap may be obtained in the material 103 upon providing an increased dopant concentration for the extension regions 152, as indicated by the dashed line 152T, wherein, however, dopant species may also diffuse into the silicon area of the channel region 151, in which the dopant species has a significantly greater diffusivity, thereby resulting in an increased dopant concentration in or below the channel region 151. The increased P-type dopant concentration in this area, however, may result in additional transistor leakage currents and may also increase the probability of punch through events. Consequently, the dopant concentration for the extension regions 152 and thus also of the drain and source regions 153 may not be arbitrarily increased.
Consequently, a non-optimized dopant profile after forming the drain and source extension regions 152 and the drain and source regions 153 on the basis of an increased dopant concentration may make the approach of adjusting the threshold voltage of the transistor 150 on the basis of the material 103 less than desirable due to increased leakage currents and the risk of punch through.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.